The present invention relates to a voltage generating circuit that divides a potential difference between a higher potential supply and a lower potential supply to generate divided potentials, and more specifically, to a voltage generating circuit integrated into a D/A converter and a current generating circuit.
FIG. 1 is a circuit diagram of a digital-to-analog (D/A) converter 11 having a resistor string configuration which is incorporated into a semiconductor device. The D/A converter 11 divides a potential difference between a higher potential supply VDD and a lower potential supply VSS into 64 equal potentials, and generates an analog signal Aout having a potential [(VDD-VSS).times.(n/64)+VSS] corresponding to a digital signal Din. The D/A converter 11 includes a voltage dividing circuit 12 having resistors R1-R11 whose number corresponds to the 6 bit digital signal Din. The resistors R1-R11 are connected in series between a first supply line L1 for the higher potential supply VDD and a second supply line L2 for the lower potential supply VSS. The values of the resistors R1-R11 are weighted in correspondence with the bit number of the digital signal Din.
Provided that the resistor R1 has the reference resistance `1`, the resistors R2a, R2b are set to have the resistance `1`, the resistors R3a, R3b to have the resistance `2`, the resistors R4a, R4b to have the resistance `4`, and the resistors R5-R11 to have the resistance `8`.
The resistors R2a-R4a on the higher potential supply VDD are connected in parallel with switches SW1a-SW3a, respectively. The resistors R2b-R4b on the lower potential supply VSS are connected in parallel with switches SW1b-SW3b, respectively. The D/A converter 11 controls the switches SW1a-SW3a and SW1b-SW3b to turn on or off in accordance with the lower three bits of the digital signal Din. If the lower three bits are `000`, for example, the D/A converter 11 switches the switches SW1b-SW3b off and the switches SW1a-SW3a on. This sets the resistance between a node N2 and the second supply line L2 to `0` (the resistance between the first supply line L1 and a node N1 is set to `8`). If the lower three bits of the digital signal Din are `001`, the D/A converter 11 switches the switches SW1b, SW2b, and SW3a off and the switches SW1a, SW2a, and SW3b on. This sets the resistance between the node N2 and the second supply line L2 to `1` (the resistance between the first supply line L1 and the node N1 is set to `7`).
The combined resistance of the resistors R5-R11 connected in series is always constant (8.times.7=56). The D/A converter 11 holds the resistance between the first supply line L1 and the second supply line L2 always at a constant value `64` by controlling the switches. Further, in accordance with the lower three bits of the digital signal Din, the D/A converter 11 varies the resistance between the first supply line L1 and the node N1 and the resistance between the node N2 and the second supply line L2 in a `1` by `1` manner.
The potential difference between the node N1 and the node N2 is determined by the potential difference between the first supply line L1 and the second supply line L2, the resistance between the first supply line L1 and the node N1, the resistance between the nodes N1 and N2, and the resistance between the node N2 and the second supply line L2. Accordingly, the D/A converter 11 varies the potential difference between the node N1 and N2 in steps of 1/64 of the potential difference between the first supply line L1 and the second supply line L2, in accordance with the lower three bits of the digital signal Din. The potential difference between the node N1 and N2 is equally divided by the resistors R5-R11 into a plurality of (in this case 8) divided potentials. The D/A converter 11 switches one of the switches SW4-SW11 on in accordance with the upper three bits of the digital signal Din. The one divided potential thus generated is supplied to an amplifier 13 through the switch SW4-SW11 that is on. The amplifier 13 outputs the analog signal Aout.
The noninverting input terminal of the amplifier 13 is connected to the lower potential supply VSS through a capacitor C1. The capacitor C1 is provided to reduce noise generated during the switching of the switches SW4-SW11.
The switch SW1a connected in parallel with the resistor R2a includes, as shown in FIG. 2, a P-channel MOS (PMOS) transistor 14 and an N-channel MOS (NMOS) transistor 15, which are connected in parallel each other. The gate of the PMOS transistor 14 is supplied with a control signal Cont that is inverted by an inverter 16. The gate of the NMOS transistor 15 is supplied with the control signal Cont. Both the transistors 14, 15 simultaneously switch on or off in response to the control signal Cont. The other switches SW1b, SW2a-SW3b have the same configuration as the switch SW1a.
However, the resistance of each of the switches SW1a-SW3b when turned on is not zero ohms. Consequently, the resistors R2a-R4b are each connected in parallel with the resistances of the switches SW1a-SW3b when turned on. As the result, the potential difference between the node N1 and the node N2 varies. This variation makes it difficult to obtain an accurate analog potential having 64 discrete values, consequently making the operation of the semiconductor device unstable.
The semiconductor device is provided with a current generating circuit for supplying a predetermined current to its inner circuits. It is difficult to obtain a stabilized current due to the variation of the power supply voltage supplied to the current generating circuit. This also adversely affects the operation of the semiconductor device.
It is therefore an object of the present invention to provide a D/A converter and a current generating circuit which overcome those difficulties and allow for stable operation of the semiconductor device.